/*
 * Copyright (c) 2024 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32N6_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32N6_RESET_H_

#include "stm32-common.h"

/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1	0x210
#define STM32_RESET_BUS_AHB2	0x214
#define STM32_RESET_BUS_AHB3	0x218
#define STM32_RESET_BUS_AHB4	0x21C
#define STM32_RESET_BUS_AHB5	0x220
#define STM32_RESET_BUS_APB1L	0x224
#define STM32_RESET_BUS_APB1H	0x228
#define STM32_RESET_BUS_APB2	0x22C
#define STM32_RESET_BUS_APB4L	0x234
#define STM32_RESET_BUS_APB4H	0x238
#define STM32_RESET_BUS_APB5	0x23C

#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32N6_RESET_H_ */
